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| 184pin Registered DDR SDRAM DIMMs based on 512Mb B ver. (TSOP) This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil. TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based Registered DIMM series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES * * * * * * * * JEDEC Standard 184-pin dual in-line memory module (DIMM) Two ranks 256M x 72 organization Error Check Correction (ECC) Capability 2.5V 0.2V VDD and VDDQ Power supply for DDR333 and below All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 100/133 MHz DLL aligns DQ and DQS transition with CK transition Programmable CAS Latency: DDR200(2 clock), DDR266(2, 2.5 clock) * * * * * * * Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Edge-aligned DQS with data outs and Center-aligned DQS with data inputs Auto refresh and self refresh supported 8192refresh cycles / 64ms Serial Presence Detect (SPD) with EEPROM Built with 512Mb DDR SDRAMs in 400 mil TSOP II packages Lead-free product listed for each configuration (RoHS compliant) ADDRESS TABLE Organization 2GB 128M x 72 Ranks 2 SDRAMs 128Mb x 4 (Stacked) # of DRAMs 36 # of row/bank/column Address 13(A0~A12)/2(BA0,BA1)/12(A0~A9,A11,A12) Refresh Method 8K / 64ms PREFORMANCE Part-Number Suffix Speed Bin CL - tRCD- tRP CL=3 Max Clock Frequency CL=2.5 CL=2 -K DDR266A 2-3-3 133 133 -H DDR266B 2.5-3-3 133 133 -L DDR200 2-2-2 100 100 Unit CK MHz MHz MHz Rev. 1.1 / May. 2005 1 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 184pin Registered DDR SDRAM DIMMs ORDERING INFORMATION Part Number HYMD525G726BS4-K/H/L HYMD525G726BSP4-K/H/L HYMD525G726BS4M-K/H/L HYMD525G726BSP4M-K/H/L Density 2GB 2GB 2GB 2GB Organization 256Mb x 4 (stacked) 256Mb x 4 (stacked) 256Mb x 4 (stacked) 256Mb x 4 (stacked) # of DRAMs 36 36 36 36 Material Normal Pb-free1 Normal Pb-free1 DIMM Dimension 133.35 x 43.18 x 6.81 [mm3] 133.35 x 30.48 x 6.81 [mm3] Note: 1. The "Pb-free" products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability. * These products are built with HY5DU124(8,16)22BT[P], the Hynix DDR SDRAM component. Rev. 1.1 /May. 2005 2 184pin Registered DDR SDRAM DIMMs PIN DESCRIPTION Pin CK0, /CK0 /CS0, /CS1 CKE0, CKE1 /RAS, /CAS, /WE A0 ~ A13 A10/AP BA0, BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS8 DM0~8 Pin Description Differential Clock Inputs Chip Select Inputs Clock Enable Inputs Commend Sets Inputs Address Inputs Address Input/Autoprecharge Bank Address Data Inputs/Outputs Data Check bits Data Strobes Data-in Masks Pin VDD VDDQ VSS VREF VDDSPD VDDID SA0~SA2 SCL SDA DU NC TEST Pin Description Power Supply for Core and I/O Power Supply for DQs Ground Input/Output Reference Power Supply for SPD VDD, VDDQ Level Detection SPD Address Inputs SPD Clock Input SPD Data Input/Output Do not Use No Connect Reserved for test equipment use PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ NC,CK1 NC,/CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Name VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC,/CS2 DQ48 DQ49 VSS NC,/CK2 NC,CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Name VSS DQ4 DQ5 VDDQ DM0,DQS9 DQ6 DQ7 VSS NC NC,TEST NC,/FETEN VDDQ DQ12 DQ13 DM1,DQS10 VDD DQ14 DQ15 CKE1 VDDQ NC,BA2 DQ20 NC,A12 VSS DQ21 A11 DM2,DQS11 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Name VSS A6 DQ28 DQ29 VDDQ DM3,DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8,DQS17 A10 CB6 VDDQ CB7 Key VSS DQ36 DQ37 VDD DM4,DQS13 DQ38 DQ39 VSS DQ44 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name /RAS DQ45 VDDQ /CS0 /CS1 DM5,DQS14 VSS DQ46 DQ47 NC,/CS3 VDDQ DQ52 DQ53 NC,A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7,DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Rev. 1.1 /May. 2005 3 184pin Registered DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB, 256Mb x 72 ECC Registered DIMM: HYMD525G726BS[P]4[M] VSS /RS1 /RS0 DQS0 DQ00 DQ01 DQ02 DQ03 DQS1 DQ08 DQ09 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB0 CB1 CB2 CB3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DQS /CS I/O0 I/O1 I/O2 I/O3 DM DQS /CS I/O0 I/O1 I/O2 I/O3 DM DM0/DQS9 D0 D18 DQ04 DQ05 DQ06 DQ07 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D9 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D27 DM1/DQS10 DM D1 D19 DQ12 DQ13 DQ14 DQ15 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D10 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D28 DM2/DQS11 DM D2 D20 DQ20 DQ21 DQ22 DQ23 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D11 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D29 DM3/DQS12 DM D3 D21 DQ28 DQ29 DQ30 DQ31 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D12 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D30 DM4/DQS13 DM D4 D22 DQ36 DQ37 DQ38 DQ39 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D13 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D31 DM5/DQS14 DM D5 D23 DQ44 DQ45 DQ46 DQ47 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D14 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D32 DM6/DQS15 DM D6 D24 DQ52 DQ53 DQ54 DQ55 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D15 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D33 DM7/DQS16 DM D7 D25 DQ60 DQ61 DQ62 DQ63 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D16 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D34 DM8/DQS17 DM D8 D26 CB4 CB5 CB6 CB7 VDDSPD DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D17 DQS /CS I/O0 I/O1 D0 I/O2 I/O3 DM D35 /S0 /S1 BA0-BA1 A0-A12 /RAS /CAS CKE0 CKE1 /WE PCK /PCK Serial PD DO-D35 DO-D35 WP DO-D35 R E G I S T E R /RS0->/CS : SDRAMs D0-D17 /RS1->/CS : SDRAMs D18-D35 RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D35 VDDQ VDD VREF Serial PD SCL A0 A1 A2 SDA RA0-RA12-> : A0->A12 : SDRAMs D0-D35 SA0 SA1SA2 DO-D35 VSS /RRAS->/RAS : SDRAMs D0-D35 /RCAS->/CAS : SDRAMs D0-D35 VDDID Strap:see Note 4 Note : RCKE0->CKE : SDRAMs D0-D17 1. DQ-to-I/O wiring may be changed within a byte. RCKE1->CKE : SDRAMs D18-D35 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. /RWE->WE : SDRAMs D0-D35 /RESET CKO, /CKO------PLL* * Wire per Clock Loading Table/Wiring Diagram 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ) : STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD VDDQ 5. Address and control resistors should be 22 Ohms. 6. Each Chip Select and CKE pair alternate between decks for thermal enhancement. Rev. 1.1 /May. 2005 4 184pin Registered DDR SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS1 Parameter Operating Temperature (Ambient) Storage Temperature Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Voltage on inputs relative to Vss Voltage on I/O pins relative to Vss Output Short Circuit Current Soldering Temperature Time Symbol TA TSTG VDD VDDQ VINPUT VIO IOS TSOLDER Rating 0 ~ 70 -55 ~ 150 -1.0 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 -0.5 ~3.6 50 260 10 oC Unit oC oC V V V V mA Sec Note: 1. Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input Leakage Current Output Leakage Current Normal Strength Output Driver Output High Current (min VDDQ, min VREF, min VTT) (min VDDQ, max VREF, max VTT) Half Strength Out- Output High Current put Driver (min VDDQ, min VREF, min VTT) (VOUT=VTT 0.68) Output Low Current Symbol VDD VDDQ VIH VIL VTT VREF VIN(DC) VID(DC) VI(RATIO) ILI ILO IOH IOL IOH IOL Min 2.3 2.3 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ -0.3 0.36 0.71 -2 -5 -16.8 16.8 -13.6 13.6 Typ. 2.5 2.5 VREF 0.5*VDDQ - Max 2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ VDDQ+0.3 VDDQ+0.6 1.4 2 5 - Unit V V V V V V V V uA uA mA mA mA mA Note 1 3 4 5 6 7 8 (VOUT=VTT 0.84) Output Low Current (min VDDQ, max VREF, max VTT) Note: 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value. 4. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 6. VIN=0 to VDD, All other pins are not tested under VIN =0V. 7. DQs are disabled, VOUT=0 to VDDQ. Rev. 1.1 /May. 2005 5 184pin Registered DDR SDRAM DIMMs IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) 2GB, 256Mb x 72 ECC Registered DIMM: HYMD525G726BS[P]4[M] Symbol Test Condition One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE= High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE=<0.2V; External clock on; tCK =tCK(min) Normal Low Power Speed -K 3530 -H 3530 -L 3170 Unit Note IDD0 mA IDD1 IDD2P IDD2F IDD3P 4070 810 1910 882 4070 810 1910 882 3890 810 1910 882 mA mA mA mA IDD3N 2090 2090 2090 mA IDD4R 4970 4970 4430 mA IDD4W 4970 4970 4430 mA IDD5 IDD6 IDD7 6050 630 540 8210 6050 630 540 8210 5690 630 540 mA mA mA mA Four bank interleaving with BL=4 Refer to the following page for detailed test condition 6770 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 /May. 2005 6 184pin Registered DDR SDRAM DIMMs AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.31 0.7 0.5*VDDQ-0.2 Max VREF - 0.31 VDDQ + 0.6 0.5*VDDQ+0.2 Unit V V V V 1 2 Note Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF OUTPUT LOAD CIRCUIT VTT RT=50 Output Zo=50 VREF CL=30pF Rev. 1.1 /May. 2005 7 184pin Registered DDR SDRAM DIMMs CAPACITANCE (TA=25oC, f=100MHz) 2GB: HYMD525G72BS[P]4[M] Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance Data Input / Output Capacitance /RAS, /CAS, /WE CKE0, CKE1 /CS0, /CS1 CK0, /CK0 DQ0 ~ DQ63, DQS0 ~ DQS17 CB0 ~ CB7 Pin A0 ~ A12, BA0, BA1 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIO1 CIO2 Min 7 7 7 7 7 11 11 Max 14 14 14 14 14 17 17 Unit pF pF pF pF pF pF pF Rev. 1.1 /May. 2005 8 184pin Registered DDR SDRAM DIMMs AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted) Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Internal Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time22 CL = 3 System Clock Cycle CL = 2.5 Time24 CL = 2 Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR DDR400B Min 55 70 40 tRCD or tRASmin 15 10 1 15 15 2 (tWR/ tCK) + (tRP/tCK) 5 tCK tCH tCL tAC 0.45 0.45 -0.7 -0.55 tHP -tQHS min (tCL,tCH) Max 70K DDR333 Min 60 72 42 tRCD or tRASmin 18 12 1 18 15 1 (tWR/ tCK) + (tRP/tCK) 6 7.5 0.45 0.45 -0.7 -0.6 tHP -tQHS min (tCL,tCH) Max 70K DDR266A Min 65 75 45 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK) + (tRP/tCK) 7.5 7.5 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) Max 120K DDR266B Min 65 75 45 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK) + (tRP/tCK) 7.5 10 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) Max 120K DDR200 Min 70 80 50 tRCD or tRASmin 20 15 1 20 15 1 (tWR/ tCK) + (tRP/tCK) 8.0 10 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) Max 120K UNIT ns ns ns ns ns ns tCK ns ns tCK tDAL - - - - - tCK 10 0.55 0.55 0.7 0.55 0.4 0.5 12 12 0.55 0.55 0.7 0.6 0.45 0.55 12 12 0.55 0.55 0.75 0.75 0.5 0.75 12 12 0.55 0.55 0.75 0.75 0.5 0.75 12 12 0.55 0.55 0.75 0.75 0.6 0.75 ns ns tCK tCK ns ns ns ns ns ns ns DQS-Out edge to Clock tDQSCK edge Skew DQS-Out edge to DataOut edge Skew21 Data-Out hold time from DQS20 Clock Half Period19,20 Data Hold Skew Factor20 Valid Data Output Window tDQSQ tQH tHP tQHS tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ Rev. 1.1 /May. 2005 9 184pin Registered DDR SDRAM DIMMs - Continue Parameter Data-out high-impedance window from CK,/CK10 Data-out low-impedance window from CK, /CK10 Input Setup Time (fast slew rate)14,16-18 Input Hold Time (fast slew rate)14,16-18 Input Setup Time (slow slew rate)15-18 Input Hold Time (slow slew rate)15-18 Input Pulse Width17 Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQSIn DQS falling edge to CK setup time DQS falling edge hold time from CK DQ & DM input setup time25 DQ & DM input hold time25 DQ & DM Input Pulse Width17 Read DQS Preamble Time Read DQS Postamble Time Symbol DDR400B Min -0.7 -0.7 0.6 0.6 0.7 0.7 2.2 0.35 0.35 0.72 0.2 0.2 0.4 0.4 1.75 0.9 0.4 0 Max 0.7 0.7 1.25 1.1 0.6 0.6 7.8 DDR333 Min -0.7 -0.7 0.75 0.75 0.8 0.8 2.2 0.35 0.35 0.75 0.2 0.2 0.45 0.45 1.75 0.9 0.4 0 0.25 0.4 2 75 200 Max 0.7 0.7 1.25 1.1 0.6 0.6 7.8 DDR266A Min -0.75 -0.75 0.9 0.9 1.0 1.0 2.2 0.35 0.35 0.75 0.2 0.2 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 75 200 Max 0.75 0.75 1.25 1.1 0.6 0.6 7.8 DDR266B Min -0.75 -0.75 0.9 0.9 1.0 1.0 2.2 0.35 0.35 0.75 0.2 0.2 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 75 200 Max 0.75 0.75 1.25 1.1 0.6 0.6 7.8 DDR200 Min -0.8 -0.8 1.1 1.1 1.1 1.1 2.5 0.35 0.35 0.75 0.2 0.2 0.6 0.6 2 0.9 0.4 0 0.25 0.4 2 80 200 Max 0.8 0.8 1.25 1.1 0.6 0.6 7.8 UNIT tHZ tLZ tIS tIH tIS tIH tIPW tDQSH tDQSL tDQSS tDSS tDSH tDS tDH tDIPW tRPRE tRPST ns ns ns ns ns ns ns tCK tCK tCK tCK tCK ns ns ns tCK tCK ns tCK tCK tCK ns tCK us Write DQS Preamble Setup Time12 tWPRES Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to non-Read command23 Exit Self Refresh to Read command Average Periodic Refresh Interval13,25 11 tWPREH 0.25 tWPST tMRD tXSNR tXSRD tREFI 0.4 2 75 200 - Rev. 1.1 /May. 2005 10 184pin Registered DDR SDRAM DIMMs Note: 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Output (VOUT) 30 pF Figure: Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is recognized as LOW. 7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference level for signals other than CK, /CK is VREF. 8. The output timing reference voltage level is VTT. 9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 14. For command/address input slew rate 1.0 V/ns. 15. For command/address input slew rate 0.5 V/ns and 1.0 V/ns 16. For CK & /CK slew rate 1.0 V/ns (single-ended) 17. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 18. Slew Rate is measured between VOH(ac) and VOL(ac). 19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. Rev. 1.1 /May. 2005 11 184pin Registered DDR SDRAM DIMMs 20.tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 21. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 22. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5 ns tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks = ((2) + (3)) clocks = 5 clocks 23. In all circumstances, tXSNR can be satisfied using tXSNR = tRFCmin + 1*tCK 24. The only time that the clock frequency is allowed to change is during self-refresh mode. 25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. Rev. 1.1 /May. 2005 12 184pin Registered DDR SDRAM DIMMs SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS The following tables are described specification parameters that required in systems using DDR devices to ensure proper performannce. These characteristics are for system simulation purposes and are guaranteed by design. Input Slew Rate for DQ/DM/DQS AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) Symbol DCSLEW min 0.5 (Table a.) DDR333 min 0.5 max 4.0 DDR266 min 0.5 max 4.0 DDR200 min 0.5 max 4.0 UNIT Note DDR400 max 4.0 V/ns 1,12 Address & Control Input Setup & Hold Time Derating (Table b.) Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns Delta tIS 0 +50 +100 Delta tIH 0 0 0 UNIT ps ps ps (Table c.) UNIT ps ps ps Note 11 11 11 (Table d.) Note 9 9 9 DQ & DM Input Setup & Hold Time Derating Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns Delta tDS 0 +75 +150 Delta tDH 0 0 0 DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate Input Slew Rate 0.0 ns/V 0.25 ns/V 0.5 ns/V Delta tDS 0 +50 +100 Delta tDH 0 +50 +100 UNIT ps ps ps Note 10 10 10 (Table e.) Note 1,3,4,6,7,8 2,3,4,6,7,8 Output Slew Rate Characteristics (for x4, x8 Devices) Slew Rate Characteristic Pullup Slew Rate Pulldown Slew Rate Typical Range (V/ns) 1.2 - 2.5 1.2 - 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Output Slew Rate Characteristics (for x16 Device) (Table f.) Slew Rate Characteristic Pullup Slew Rate Pulldown Slew Rate Typical Range (V/ns) 1.2 - 2.5 1.2 - 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Note 1,3,4,6,7,8 2,3,4,6,7,8 (Table g.) DDR200 min 0.71 max 1.4 Note 5,12 Output Slew Rate Matching Ratio Characteristics Slew Rate Characteristic Parameter Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR266A min max DDR266B min - max - Rev. 1.1 /May. 2005 13 184pin Registered DDR SDRAM DIMMs Note: 1. Pullup slew rate is characterized under the test conditions as shown in below Figure. Test Point Output (VOUT) 50 VSSQ Figure: Pullup Slew rate 2. Pulldown slew rate is measured under the test conditions shown in below Figure. VDDQ Output (VOUT) 50 Test Point Figure: Pulldown Slew rate 3. Pullup slew rate is measured between (VDDQ/2 - 320 mV 250mV) Pulldown slew rate is measured between (VDDQ/2 + 320mV 250mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example: For typical slew, DQ0 is switching For minimum slew rate, all DQ bits are switching worst case pattern For maximum slew rate, only one DQ is switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. 4. Evaluation conditions Typical: 25 oC (Ambient), VDDQ = nominal, typical process Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process 5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 6. Verified under typical conditions for qualification purposes. 7. TSOP-II package devices only. 8. Only intended for operation up to 256 Mbps per pin. 9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b. The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. 10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c & d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(slew Rate2)} For example: If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100ps. 11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions. 12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. Rev. 1.1 /May. 2005 14 184pin Registered DDR SDRAM DIMMs SIMPLIFIED COMMAND TRUTH TABLE Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit Entry Exit Entry Exit CKEn-1 H H H H H H H H H H L H L H L CKEn X X X X X X X X H L H L H L H /CS L L H L L L L L L L L H L H L H L H L /RAS L L X H L H H L H L L X H X H X H X V X /CAS L L X H H L L H H L L X H X H X H X V /WE L L X H H H L L L H H X H X H X H X V X X X CA CA X RA L H L H H L X X ADDR A10/AP OP code OP code X BA Note 1,2 1,2 1 V V V X V 1 1 1,3 1 1,4 1,5 1 1 1 1 1 1 1 1 1 1 1 1 Precharge Power Down Mode Active Power Down Mode ( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note: 1. DM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. WRITE MASK TRUTH TABLE Function Data Write Data-In Mask Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. CKEn-1 H H CKEn X X /CS, /RAS, /CAS, /WE X X DM L H ADDR A10/AP X X BA Note 1 1 Rev. 1.1 /May. 2005 15 184pin Registered DDR SDRAM DIMMs 2GB, 256Mb x 72 ECC Registered DIMM: R/C C - HYMD525G726BS[P]4 PACKAGE DIMENSIONS Unit: Millimeters Inches Front 133.35 5.25 (2X)4.00 .157 43.18 1.7 Register PLL Register Back 6.81 .268max Side 1.27+/-0.10 0.05+/-0.004 Rev. 1.1 /May. 2005 (Front) 16 184pin Registered DDR SDRAM DIMMs 2GB, 256Mb x 72 ECC Registered DIMM: R/C N - HYMD525G726BS[P]4M PACKAGE DIMENSIONS Front 133.35 5.25 Unit: Millimeters Inches Register 30.48 1.2 PLL Back Side 6.81 TSOP 0.268max Register (Front) 1.27 0.050 Note) All dimension are typical unless otherwise stated. Millimeters Inches Rev. 1.1 /May. 2005 17 184pin Registered DDR SDRAM DIMMs REVISION HISTORY Revision 1.0 1.1 History First Version Release - Datasheet coverage is changed from an individual module part to a component based module family Corrected PIN DESCRIPTION and PIN ASSIGNMENT Tables Date Feb. 2005 May. 2005 Remark Rev. 1.1 /May. 2005 18 |
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